Semiconductor triode device having a compound-semiconductor channel layer

ABSTRACT

A semiconductor triode comprises a gate electrode provided on a channel layer, wherein there is interposed an insulating metal oxide layer between a top surface of the channel layer and the gate electrode.

CROSS-REFERENCE TO RELATED APPLICATION

[0001] The present application is based on Japanese priority applicationNo. 2000-095895 filed on Mar. 30, 2000, the entire contents of which arehereby incorporated by reference.

BACKGROUND OF THE INVENTION

[0002] The present invention generally relates to semiconductor devicesand more particularly to a high-speed semiconductor triode having acompound-semiconductor channel layer.

[0003] Compound-semiconductor triodes, typical examples being a MESFETor a HEMT, is characterized by high operational speed due to highelectron mobility of compound-semiconductor material used for the activelayer thereof. Thus, such compound-semiconductor triodes are usedextensively for high-frequency or ultra high-frequency applicationsincluding GHz band application.

[0004] In such compound-semiconductor triodes, too, there holds thescaling law, and efforts are made to reduce the gate length as much aspossible for maximizing the operational speed.

[0005] A high-speed semiconductor triode having a short gate length isdesigned, in order to suppress the short-channel effect as much aspossible, such that carriers are transported through a shallow, limitedsurface region of a compound-semiconductor layer used for the activelayer of the semiconductor triode.

[0006] Thus, the quality of the crystal of the compound-semiconductorlayer, particularly the quality of the surface part of thecompound-semiconductor layer used for the active layer is extremelyimportant for the operational characteristic of the semiconductortriode.

[0007]FIG. 1 shows the construction of a HEMT 10 according to a relatedart.

[0008] Referring to FIG. 1, the HEMT 10 is constructed on asemi-insulating InP substrate 11 and includes a channel layer 12 ofundoped InGaAs formed epitaxially on the InP substrate 11 and anelectron-supplying layer 13 of n-type InAlAs formed also epitaxially onthe channel layer 12. A cap layer 14 of n⁺-type InGaAs is formed on theelectron-supplying layer 13 epitaxially, and an opening 14A exposing thesurface of the electron-supplying layer 13 is formed in the cap layer14. Further, a gate electrode 15 Is formed on the exposed surface of theelectron-supplying layer 13 in the opening 14A.

[0009] In the illustrated example, the gate electrode 15 is a so-calledmushroom type or T-type electrode and includes a Ti layer 15A making aSchottky contact with the exposed electron-supplying layer 13, a Ptdiffusion-barrier layer 15B formed on the Ti layer 15A, and alow-resistance Au electrode layer 15C having the mushroom-shape andformed on the Pt layer 15B.

[0010] By using the Au electrode 15C with such a mushroom-shape, itbecomes possible to reduce the resistance of the gate electrode 15 whileminimizing the gate-length of the gate electrode 15 simultaneously. ThePt diffusion barrier layer 15B, on the other hand, blocks the diffusionof Au atoms from the Au electrode into the electron-supplying layer 13.Further, the Ti layer 15A provided between the electron-supplying layer13 and the Pt layer 15B improves the adherence of the Pt layer 15B tothe electron-supplying layer 13.

[0011] In the HEMT 10 of FIG.1, it should further be noted that ohmicelectrodes 16 and 17 are formed on the InGaAs cap layer 14 incorrespondence to contact regions 14B and 14C respectively. The ohmicelectrode 16 constitutes a non-alloy ohmic electrode and includes a Tilayer 16A forming an ohmic contact with the n⁺-type cap layer 14, a Ptdiffusion barrier layer 16B formed on the Ti layer 16A and alow-resistance Au electrode layer 16C formed on the Pt diffusion barrierlayer 16B. The ohmic electrode 17 has a similar construction.

[0012] Further, the HEMT of FIG.1 includes an SiN passivation film 18covering the exposed part of the electron-supplying layer 13 and thecontact regions 14B and 14C.

[0013] In such a conventional compound-semiconductor triodes, includingalso MESFETs in addition to HEMTs, the gate electrode 15 makes a directcontact with the semiconductor layer, and thus, there is a substantialrisk that Ti atoms may cause a diffusion from the Ti adhesion layer 15Aof the gate electrode 15 into the n-type electron-supplying layer 13 andfurther into the channel layer 12 underneath the electron-supplyinglayer 13. When such a diffusion of Ti is caused in the semiconductorlayers constituting the channel of the triode, the thresholdcharacteristic of the device is deteriorated seriously.

[0014]FIG. 2 shows such a change of the threshold voltage Vth for thecase such a diffusion of Ti is caused from a gate electrode into achannel layer in the case of a conventional MESFET.

[0015] Referring to FIG.2, it can be seen that the threshold voltage Vthincreases generally linearly with the depth of penetration of the Tiatoms, and that the threshold voltage Vth changes as much as 0.1V withthe penetration of only 1 nm in depth. Thus, there is a need for astructure, in compound-semiconductor triodes such as HEMTs or MESFETs,which is effective for suppressing the diffusion of TI atoms from theelectrode into the compound-semiconductor layer.

[0016] Conventionally, it has been practiced in the art ofcompound-semiconductor Schottky diode to interpose a metal oxide layerbetween the Schottky electrode and the compound-semiconductor layer forsuppressing the diffusion of metal elements from the Schottky electrodeto the compound-semiconductor layer, and hence to suppress the change ofSchottky barrier height. In relation to this, reference may be made toJapanese Laid-Open Patent Publication 4-69974.

[0017] In this prior art reference, the use of TiOx formed as a resultof oxidation of the surface of the metallic Ti layer is described as anexample of such a metal oxide layer.

[0018]FIG. 3 shows the effect of Ti diffusion on the Schottky barrierheight φ_(B) of a Schottky diode.

[0019] Referring to FIG. 3, it can be seen that there occurs nosubstantial change of Schottky barrier height φ_(B) even when the Tiatoms have penetrated into the semiconductor layer with the thickness ofseveral nanometers. Thus, it is concluded that, in the case of asemiconductor Schottky diode, the use of such a metal oxide layerbetween the semiconductor layer and the Schottky electrode causes nosubstantial change of diode characteristic.

[0020] In the case of a compound-semiconductor triodes such as a HEMT ora MESFET, on the other hand, the situation is different, and penetrationTi of only 1 nm depth in the channel region causes a serious change ofthe threshold voltage Vth.

[0021] In the fabrication process of a semiconductor triode, variousannealing steps are applied after a Schottky electrode is formed on achannel layer as a gate electrode. Thus, the foregoing variation of thethreshold voltage Vth, caused as a result of Ti penetration, remains asubstantial problem in the art of compound-semiconductor triodes.

SUMMARY OF THE INVENTION

[0022] Accordingly, it is a general object of the present invention toprovide a novel and useful compound-semiconductor triode wherein theforegoing problems are eliminated.

[0023] Another and more specific object of the present invention is toprovide a high-speed compound-semiconductor triode stable againstthermal annealing process.

[0024] Another object of the preset invention is to provide asemiconductor triode, comprising:

[0025] a semiconductor layer including a channel layer;

[0026] a first ohmic electrode supplying carriers into said channellayer;

[0027] a second ohmic electrode collecting carriers from said channellayer; and

[0028] a gate electrode controlling a flow of said carriers through saidchannel layer from said first ohmic electrode to said second ohmicelectrode, said gate electrode including an insulating metal oxide filmformed at an interface to a surface of said semiconductor layer.

[0029] According to the present invention, the threshold characteristicof the semiconductor triode is stabilized substantially by interposingthe metal oxide film. Further, such a structure is advantageous forimproving the yield of production of the device.

[0030] Preferably, the metal oxide film is formed of any of an oxide ofa metal element selected from the group consisting of Ti, Co, Ni, Ta,Pr, Hf, Zr and Pd. The metal oxide film may be formed also at theinterface between the first ohmic electrode and the semiconductor layerand the interface between the second ohmic electrode and thesemiconductor layer. Preferably, the metal oxide film has a thicknessallowing carrier tunneling therethrough. The metal oxide film may beprovided so as to cover the surface of the semiconductor layercontinuously from the first ohmic electrode to the gate electrode andfrom the gate electrode to the second ohmic electrode. The semiconductortriode of the present invention includes a HEMT and a MESFET.

[0031] Other objects and further features of the present invention willbecome apparent from the following detailed description when read inconjunction with the attached drawings.

BRIEF DESCRIPTION OF THE DRAWINGS

[0032]FIG. 1 is a diagram showing the construction of a HEMT accordingto a related art;

[0033]FIG. 2 is a diagram showing the relationship between the thresholdcharacteristic and metal diffusion for the HEMT of FIG. 1;

[0034]FIG. 3 is a diagram showing the relationship between the Schottkybarrier height and metal diffusion for a conventional Schottky diode;

[0035]FIG. 4 is a diagram showing the construction of a HEMT accordingto a first embodiment of the present invention;

[0036] FIGS. 5A-5E are diagrams showing the fabrication process of theHEMT of FIG. 4;

[0037]FIG. 6 is a diagram showing the relationship between the thresholdcharacteristic and annealing temperature for the HEMT of FIG. 4 incomparison with a conventional HEMT;

[0038]FIG. 7 is a diagram showing the relationship between the ohmiccontact resistance and annealing temperature for the HEMT of FIG. 4 incomparison with a conventional HEMT;

[0039] FIGS. 8A-8F are diagrams showing the fabrication process of aHEMT according to a second embodiment of the present invention; and

[0040] FIGS. 9A-9C are diagrams showing the fabrication process of aMESFET according to a third embodiment of the present invention.

DETAILED DESCRIPTION OF THE INVENTION [First Embodiment]

[0041]FIG. 4 shows the construction of a HEMT 20 according to a firstembodiment of the present invention.

[0042] Referring to FIG. 4, the HEMT 20 is constructed on asemi-insulating InP substrate 21 carrying thereon a buffer layer 21A ofundoped InAlAs with a thickness of about 200 nm, and includes a channellayer 22 of undoped InGaAs formed on the buffer layer 21A epitaxiallywith a thickness of about 25 nm and an electron supplying layer 23 ofn-type InAlAs formed on the channel layer 22 with a carrier density ofabout 2×10¹⁸ cm⁻³ and a thickness of about 25 nm, wherein the electronsupplying layer 23 is covered with a cap layer 24 of InGaAs having athickness of about 50 nm and a carrier density of about 1×10¹⁹ cm⁻³.Further, the cap layer 24 is formed with an opening 24A exposing theelectron-supplying layer 23 in correspondence to a gate electrode 25.

[0043] It should be noted that the gate electrode 25 is a so-calledmushroom type or T-type electrode and includes a Ti layer 25A having athickness of about 1 nm provided in contact with the exposed surface ofthe electron-supplying layer in the opening 24A, a Pt barrier layer 25Bformed on the Ti layer 25A with a thickness of about 10 nm, and alow-resistance Au electrode layer 25C formed on the Pt layer 25B with athickness of about 200 nm, wherein the Au electrode layer 25Cconstitutes the expanded top part of the mushroom structure. Further,the HEMT 20 of FIG. 4 includes a TiO₂ film 29 formed between the gateelectrode 25 and the electron-supplying layer with a thickness of about4 nm.

[0044] By providing the low-resistance Au electrode layer 25C for theexpanded top part of the mushroom electrode 25, it becomes possible tominimize the gate length of the electrode 25 and simultaneously the gateresistance. Further, the Pt barrier layer 25B blocks the diffusion of Auatoms from the electrode layer 25C into the electron-supplying layer 23.The Ti layer 25A and the TiO₂ film 29 improve the adherence between theelectron-supplying layer 23 and the Pt layer 25B, and hence theadherence of the gate electrode 25 to the electron-supplying layer 23.

[0045] In the HEMT 20 of FIG. 4, it should be noted that the TiO₂ film29 extends laterally and covers contact regions 24B and 24C of theInGaAs cap layer 29 continuously, wherein the contact regions 24B and24C are the separated regions of the InGaAs cap layer 29 by the opening24A.

[0046] Further, it can be seen that ohmic electrodes 26 and 27 areformed on the TiO₂ film 29 respectively in correspondence to the contactregions 24B and 24C, wherein the ohmic electrode includes a Ti layer 26Ahaving a thickness of about 1 nm provided in ohmic contact with then⁺-type InGaAs cap layer 24 via the TiO₂ film 29, and a Pt diffusionbarrier layer 26B and a low-resistance Au layer 26C having a thicknessof about 200 nm reformed consecutively on the Ti layer 26A. Thereby, thelayers 26A-26C form a non-alloy ohmic electrode. The ohmic electrode 27has a similar construction.

[0047] FIGS. 5A-5E show the fabrication process of the HEMT 20 of FIG.4.

[0048] Referring to FIG. 5A, a non-doped InGaAs layer, an n-type InAsAslayer and an n+-type InGaAs layer are formed consecutively on the bufferlayer 21 covering the InP substrate 21 respectively in correspondence tothe channel layer 22, the electron-supplying layer 23 and the cap layer24, with respective thicknesses of 25 nm, 25 nm and 50 nm. Further, thelayered semiconductor structure thus obtained is subjected to apatterning process while using a resist pattern 31, and a device region20A is formed by forming device isolation grooves 20B and 20C.

[0049] Next, in the step of FIG. 5B, the resist pattern 31 of FIG. 5A isremoved and a next resist pattern 32 having a resist opening 32A incorrespondence to a gate recess region of the HEMT 20 to be formed isprovided on the structure thus obtained. By applying a patterningprocess to the InGaAs layer 24 while using the resist pattern 32 as amask, the opening 24A is formed in the InGaAs layer 24. As a result offormation of the opening 24A, the InGaAs layer 24 is divided into thecontact regions 24B and 24C.

[0050] Next, in the step of FIG. 5C, the resist pattern 32 is removedand a Ti film is deposited on the structure thus obtained by anevaporation deposition process, such that the Ti film covers the surfaceof the device region 20A including the side wall of the device region 23and further the surface of the buffer layer 21A exposed by the deviceisolation grooves 20B and 20C, uniformly with a thickness of about 4 nm.

[0051] In the step of FIG. 5C, the Ti film thus formed is furtherconverted to a TiO₂ film 29 by applying thereto an oxygen plasmaprocess. It should be noted that the oxidation process of the Ti film toform the TiO₂ film 29 is conducted so as to obtain an effectiveinsulating film, even in such a case the “TiO₂” film thus formed hasactually a non-stoichiometric composition TiO_(x). In the descriptionhereinafter, the film 29 is designated as TiO₂ even in such a case thefilm 29 has such a non-stoichiometric composition TiO_(x).

[0052] Next, in the step of FIG. 5D, a resist pattern (not shown) havingopenings in correspondence to the ohmic electrodes 26 and 27 is formedon the TiO₂ film 29, and a conductive layer is formed on the resistpattern thus formed so as to include the foregoing resist openings, byconsecutively depositing a Ti layer, a Pt layer and an Au layer withrespective thicknesses of 1 nm, 30 nm and 200 nm. By lifting off theresist pattern and the Ti/Pt/Au layer thus deposited thereon, the ohmicelectrodes 26 and 27 are formed. It should be noted that the ohmicelectrodes 26 and 27 can achieve an effective ohmic contact with thecorresponding contact regions 24B and 24C due to the extremely smallthickness of about 4 nm of the TiO₂ film 29, which thickness beingchosen so as to allow efficient tunneling of electrons.

[0053] Next, in the step of FIG. 5E, a resist pattern (not shown) havingan opening exposing the TiO₂ film 29 in correspondence to the gaterecess region 24A is formed, and a Ti layer, a Pt layer and an Au layerare deposited consecutively thereon with respective thicknesses of 1 nm,10 nm and 200 nm. By lifting off the resist pattern and the Ti/Pt/Aulayer thereon, the gate electrode 25 described before is obtained.

[0054]FIG. 6 shows the change of the threshold voltage Vth of the HEMT40 for the case a thermal annealing process is applied at varioustemperatures in comparison with the threshold voltage Vth of the HEMT 10of FIG. 1. Further, FIG. 7 shows the change of the ohmic contactresistance Rc observed fro the HEMT 40 for the case a thermal annealingprocess is applied at various temperatures in comparison with the ohmiccontact resistance Rc of the HEMT 10 of FIG. 1.

[0055] Referring to FIG. 6, it can be seen that the threshold voltageVth of the HEMT 40 does not change at all as long as the temperature ofthe thermal annealing process Is conducted in the range of 100-300° C.,while a substantial change is observed for the threshold voltage of theHEMT 10 with the thermal annealing process of the same temperaturerange.

[0056] Similarly, it can be seen from FIG. 7 that the ohmic contactresistance Rc of the HEMT 40 does not change at all with the thermalannealing process conducted in the range of 100-300° C., while asubstantial change is observed for f the HEMT 10 with the thermalannealing process of the same temperature range.

[0057] The result of FIGS. 6 and 7 clearly indicate that the thin oxidefilm 29 provided in the HEMT 40 prevents the diffusion of the Ti atomsfrom the electrode layer 25A into the channel layer 25.

[0058] In the present embodiment, it should be noted that the process ofconverting the Ti film into the TiO₂ film is by no means limited to theoxygen plasma treatment process but may be conducted by a thermalannealing process in an oxidizing atmosphere, or alternatively in theair. In such a case, a heat treatment at a temperature of 150° C. issufficient for causing the desired conversion.

[Second Embodiment]

[0059] Next, a fabrication process of a HEMT 50 according to a secondembodiment of the present invention will be described with reference toFIGS. 8A-8D, wherein those parts corresponding to the parts describedpreviously are designated by the same reference numerals and thedescription thereof will be omitted.

[0060] Referring to FIG. 8A, the process is substantially identical withthe process of FIG. 5A and a layered semiconductor structure for thedevice region 20A is formed by stacking the semiconductor layers 22-24consecutively and patterning the same while using the resist pattern 31as a mask.

[0061] Next, in the step of FIG. 8B, the resist pattern 31 of FIG. 8A isremoved and ohmic electrodes 26 and 27 are formed on the InGaAs caplayer 24 directly.

[0062] Next, in the step of FIG. 8C, the resist pattern 32 is providedon the structure of FIG. 8B so as to cover the ohmic electrodes 26 and27, and the InGaAs cap layer 24 is patterned while using the resistpattern 32 as a mask, to form the gate recess 24A in the layer 24 incorrespondence to the resist opening in the resist pattern 32. As aresult of the formation of the gate recess 24A, the InGaAs cap layer 24is divided into the contact regions 24B and 24C.

[0063] Next, the resist pattern 32 is removed in the step of FIG. 8D anda Ti film is deposited on the exposed surface of the electron-supplyinglayer 23 by an evaporation deposition process. Further, the Ti film issubjected to a patterning process while using a resist pattern (notshown) such that the Ti film is remained on the part on which the gateelectrode is to be formed. Further, a SiN passivation film 29B isdeposited on the structure thus obtained so as to cover the Ti pattern.

[0064] Next, the SiN passivation film 29B is subjected to a patterningprocess in the step of FIG. 8E while using a resist pattern (not shown)as a mask such that the Ti pattern 29A is exposed, and the Ti pattern29A thus exposed is converted to a TiO₂ pattern 29C by applying theretoan oxygen plasma process. In this case, too, the oxidation process ofthe Ti film to form the TiO₂ pattern 29C may be conducted such that theTiO₂ pattern 29C may have a non-stoichlometric composition TiO_(x). Itshould be noted that there remains no remnant of the original Ti pattern29A after the oxidation process, and the TiO₂ pattern 29C thus obtainedforms an insulating pattern.

[0065] Next, in the step of FIG. 8F, a resist pattern (not shown) havingopenings exposing the TiO₂ pattern 29C is formed, and the gate electrode25 having the foregoing Ti/Pt/Au layered structure is formed by alift-off process using such a resist pattern.

[0066] In the HEMT 50 thus formed, the variation of the thresholdcharacteristic as a result of thermal annealing process is effectivelysuppressed similarly to the case of the HEMT 30 of the previousembodiment.

[Third Embodiment]

[0067] FIGS. 9A-9C are diagrams showing the fabrication process of aMESFET 60 according to a third embodiment of the present invention.

[0068] Referring to FIG. 9A, a semi-insulating GaAs substrate 61 issubjected to an ion implantation process of Si and there is formed ann-type channel region 61A on the surface of the substrate 61 after arapid thermal annealing process for causing a diffusion of the Si atomsthus induced. Typically, the ion implantation process may be conductedunder the acceleration voltage of 30 keV with a dose of 2×10¹² cm⁻². Thethermal annealing process may be conducted in an N₂ atmosphere at 800°C. for 30 seconds.

[0069] In the step of FIG. 9A, it should be noted that a TiO₂ film 62 isformed on the substrate 61 so as to cover the channel region 61A with auniform thickness of about 4 nm. Such a TiO₂ film 62 may be formed bydepositing a Ti film uniformly with a thickness of about 4 nm by anevaporation deposition process, followed by an oxygen plasma treatmentprocess for converting the Ti into TiO₂ film. It is not necessary thatthe TiO₂ film thus obtained has a stoichiometric composition but may behave a non-stoichiometric composition represented as TiO_(x), as long asthere remains no Ti remnant in the TiO₂ film 62 after the oxygen plasmatreatment process. As a result of such a plasma treatment process, theTiO₂ film 62 thus obtained becomes an excellent insulating film.

[0070] In the structure of FIG. 8A, a gate electrode 63 of WSi is formedon the TiO₂ film 62 with a thickness or height of about 300 nm.

[0071] Next, in the next step of FIG. 8B, an ion implantation process ofSi⁺ is conducted into the GaAs substrate 61 while using the gateelectrode 63 as a self-alignment mask, and n⁻-type LDD regions 61B and61C are formed in the substrate 61 at both lateral sides of the WSi gateelectrode 63.

[0072] Next, in the step of FIG. 8B, an SiN film is deposited on theGaAs substrate 61 by a plasma CVD process such that the SiN film coversthe WSi gate electrode 63, and side wall insulation films 63A and 63Bare formed on both lateral side walls of the gate electrode 63 as aresult of anisotropic etching process applied to the SiN film such thatthe etching proceeds generally perpendicularly to the principal surfaceof the substrate 61.

[0073] In the step of FIG. 8B, a further ion implantation process of Si⁺is conducted under an acceleration voltage of 50 keV with a dose of5×10¹² cm⁻² while using the WSi gate electrode 63 and the side wallinsulation films 63A and 63B as a self-aligned mask, and n⁺-typediffusion regions 61D and 61E are formed in the GaAs substrate 61 atouter sides of the LDD regions 61B and 61C, respectively.

[0074] Finally, contact holes are formed in the TiO₂ film 62 so as toexpose the diffusion regions 61D and 61E by a resist process, and ohmicelectrodes 64A and 64B, each having an AuGe/Au structure, are formed incorrespondence to the contact holes.

[0075] In the MESFET thus obtained, it should be noted that there occursno change of threshold voltage even when an alloying process, typicallyconducted in an N₂ atmosphere at 350° C. for 5 minutes, is applied tothe ohmic electrodes 64A and 64B, as the diffusion of metal elementsfrom the WSi gate electrode 63 into the GaAs substrate 61 is positivelyprevented by the TiO₂ film 62.

[0076] It should be noted that the TiO₂ film 29 or TiO₂ film 62 of theprevious embodiments is by no means limited to an TiO₂ film or a TiO_(x)film but various oxides of metal elements such as Co, Ni, Ta, Pr, Hf, Zrand Pd may be used for the purpose.

[0077] Further, the gate electrode formed on the metal oxide film is notlimited to the one having the Ti/Pt/Au stacked structure or the oneformed of WSi, but may have a Ti/Al stacked structure or a Ti/Mo stackedstructure.

[0078] Further, the present invention is not limited to the embodimentsdescribed heretofore, but various variations and modifications may bemade without departing from the scope of the invention.

What is claimed is:
 1. A semiconductor triode, comprising: asemiconductor layer including a channel layer; a first ohmic electrodesupplying carriers into said channel layer; a second ohmic electrodecollecting carriers from said channel layer; and a gate electrodecontrolling a flow of said carriers through said channel layer from saidfirst ohmic electrode to said second ohmic electrode, said gateelectrode including an insulating metal oxide film formed at aninterface to a surface of said semiconductor layer.
 2. A semiconductortriode as claimed in claim 1, wherein said metal oxide film is an oxideof a metal element selected from the group consisting of Ti, Co, Ni, Ta,Pr, Hf, Zr and Pd.
 3. A semiconductor triode as claimed in claim 1,wherein said insulating metal oxide has a stoichiometric composition. 4.A semiconductor triode as claimed in claim 1, wherein said insulatingmetal oxide film has a non-stoichiometric composition.
 5. Asemiconductor triode as claimed in claim 1, wherein said insulatingmetal oxide film is provided further at an interface between said firstohmic electrode and said semiconductor layer and between said secondohmic electrode and said semiconductor layer.
 6. A semiconductor triodeas claimed in claim 5, wherein said insulating metal oxide film has athickness allowing tunneling of carriers.
 7. A semiconductor triode asclaimed in claim 1 wherein said metal oxide film is provided so as tocover a surface of said semiconductor layer continuously from said firstohmic electrode to said gate electrode and from said gate electrode tosaid second ohmic electrode.
 8. A semiconductor triode as claimed inclaim 1, wherein said channel layer includes a two-dimensional electrongas.
 9. A semiconductor triode as claimed in claim 1, wherein saidchannel layer comprises a doped semiconductor layer.